構文
構文Little Endian
struct tavorprm_mt23108_type0_st
ファイル名
ファイル名構造体情報
構造体情報| No. | 名称 | 属性 | 説明 |
|---|---|---|---|
1 |
tavorprm_mt23108_type0_st | Little Endian | |
| vendor_id[0x00010] | pseudo_bit_t | Hardwired to 0x15B3 | |
| device_id[0x00010] | pseudo_bit_t | hardwired to 23108 | |
| command[0x00010] | pseudo_bit_t | PCI Command Register | |
| status[0x00010] | pseudo_bit_t | PCI Status Register | |
| revision_id[0x00008] | pseudo_bit_t | ||
| class_code_hca_class_code[0x00018] | pseudo_bit_t | ||
| cache_line_size[0x00008] | pseudo_bit_t | Cache Line Size | |
| latency_timer[0x00008] | pseudo_bit_t | ||
| header_type[0x00008] | pseudo_bit_t | hardwired to zero | |
| bist[0x00008] | pseudo_bit_t | ||
| bar0_ctrl[0x00004] | pseudo_bit_t | hard-wired to '0100 | |
| reserved0[0x00010] | pseudo_bit_t | ||
| bar0_l[0x0000c] | pseudo_bit_t | Lower bits of BAR0 (configuration space) | |
| bar0_h[0x00020] | pseudo_bit_t | Upper 32 bits of BAR0 (configuration space) | |
| bar1_ctrl[0x00004] | pseudo_bit_t | Hardwired to '1100 | |
| reserved1[0x00010] | pseudo_bit_t | ||
| bar1_l[0x0000c] | pseudo_bit_t | Lower bits of BAR1 | |
| bar1_h[0x00020] | pseudo_bit_t | upper 32 bits of BAR1 (User Access Revion - UAR - space) | |
| bar2_ctrl[0x00004] | pseudo_bit_t | Hardwired to '1100 | |
| reserved2[0x00010] | pseudo_bit_t | ||
| bar2_l[0x0000c] | pseudo_bit_t | Lower bits of BAR2 | |
| bar2_h[0x00020] | pseudo_bit_t | Upper 32 bits of BAR2 - DDR (attached memory) BAR | |
| cardbus_cis_pointer[0x00020] | pseudo_bit_t | ||
| subsystem_vendor_id[0x00010] | pseudo_bit_t | Specified by the device NVMEM configuration | |
| subsystem_id[0x00010] | pseudo_bit_t | Specified by the device NVMEM configuration | |
| expansion_rom_enable[0x00001] | pseudo_bit_t | Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. | |
| reserved3[0x0000a] | pseudo_bit_t | ||
| expansion_rom_base_address[0x00015] | pseudo_bit_t | Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. | |
| capabilities_pointer[0x00008] | pseudo_bit_t | Specified by the device NVMEM configuration | |
| reserved4[0x00018] | pseudo_bit_t | ||
| reserved5[0x00020] | pseudo_bit_t | ||
| interrupt_line[0x00008] | pseudo_bit_t | ||
| interrupt_pin[0x00008] | pseudo_bit_t | ||
| min_gnt[0x00008] | pseudo_bit_t | ||
| max_latency[0x00008] | pseudo_bit_t | ||
| reserved6[0x00100] | pseudo_bit_t | ||
| msi_cap_id[0x00008] | pseudo_bit_t | ||
| msi_next_cap_ptr[0x00008] | pseudo_bit_t | ||
| msi_en[0x00001] | pseudo_bit_t | ||
| multiple_msg_cap[0x00003] | pseudo_bit_t | ||
| multiple_msg_en[0x00003] | pseudo_bit_t | ||
| cap_64_bit_addr[0x00001] | pseudo_bit_t | ||
| reserved7[0x00008] | pseudo_bit_t | ||
| msg_addr_l[0x00020] | pseudo_bit_t | ||
| msg_addr_h[0x00020] | pseudo_bit_t | ||
| msg_data[0x00010] | pseudo_bit_t | ||
| reserved8[0x00010] | pseudo_bit_t | ||
| pcix_cap_id[0x00008] | pseudo_bit_t | ||
| pcix_next_cap_ptr[0x00008] | pseudo_bit_t | ||
| pcix_command_reg[0x00010] | pseudo_bit_t | PCIX command register | |
| pcix_status_reg[0x00020] | pseudo_bit_t | PCIX Status Register | |
| reserved9[0x00440] | pseudo_bit_t |
See Also
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